- ASIC Design Intern at NVIDIA Corporation (Summer 2012)
Clock Design Team, NVIDIA Corporation, Santa Clara, CA, USA
- Unified the clock synthesis flow of SoC processors
- Designed a CAD tool to enhance the SoC clock design and its interplay with other components
- Senior Systems and Network Administrator at Sharif University of Technology (2007-2010)
Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
- Designed and executed the new department network infrastructure (Costing over $150,000 with more than 800 Ethernet ports and core capacity of 32 Gbps)
- Led the administration team of 5 members since 2008
- Invited reviewer, Design Automation Conference (DAC), 2014 – 2018 (5 years)
- Invited reviewer, IEEE Transactions on Industrial Electronics, 2017
- Invited reviewer, Elsevier Integration, the VLSI Journal, 2016
- Invited reviewer, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2014 & 2016
- Invited reviewer, Elsevier Microelectronics Journal, 2014, 2016
- Invited reviewer, Elsevier Journal of Energy, 2015
- Reviewer, IEEE International Conference on Cloud Computing (CLOUD), 2015
- Proposal reviewer, U.S. National Science Foundation (NSF), 2014 & 2015
- Invited reviewer, World Scientific Journal of Circuits, Systems, and Computers, 2015
- Reviewer, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2014
- Invited reviewer, Reed-Muller Workshop, 2013
- Reviewer, International Symposium on VLSI Design, Automation & Test (VLSI-DAT), 2013
- Reviewer, ACM Transactions on Embedded Computing Systems (TECS), 2012
- MOS VLSI Circuit Design, University of Southern California, Spring 2014
- Digital Systems Design, Sharif University of Technology, Fall 2009
- Internet Engineering, Sharif University of Technology, Fall 2009
- Computer Structure and Language, Sharif University of Technology, Fall 2008
- PLDs and Verilog HDL, Allameh-Helli High School, Summer 2008
- Power/Thermal Analyzer for Android: Instrumented Linux kernel using SystemTap to find hardware component activities. Developed accurate power macro-models for CPU, GPU, WiFi, LCD, and flash storage. Derived transient & steady-state temperature maps for every device component. Categorized android apps based on their power/thermal effects.
- DDR2 Controller: Designed and implemented a controller based on the JEDEC standard in Verilog capable of initializing, writing and reading in sequential and burst modes. Verified in Modelsim using Denali 512Mb DDR2 IP. Synthesized and got timing closure using Design Compiler.
- Architecture Optimization: Optimized a MIPS-based processor with average speed of 4857 MIPS and 194M transistors on 20.6mm2 die in 32nm technology using SimpleScalar and CACTI (Best Design at USC), 2011
- Motion Estimator: Designed a 333MHz motion estimator circuit which included a fast adder/subtractor, register bank, and two 256-bit SRAM in 180nm. Drawn a custom layout in Cadence Virtuoso, extracted netlist and validated through SPICE simulations in Cadence Spectre, 2011
- Quantum Mapper: Design of a quantum computer technology mapper (scheduler, placer, and router) for ion-trap technology (High-level synthesis and physical design tool implemented in Java) in 2011.
- Automatic Test Pattern Generation: Developed an ATPG using Path Oriented DEcision Making (PODEM) algorithm (in C++), 2011.
- Integration, Verification and Evaluation of a Fault-Tolerant Processor based on LEON2: Involved VHDL coding, pre and post-synthesis simulation using Modelsim, developing an automated HDL fault-injector in C to produce TCL scripts for Modelsim, and synthesis using Design Compiler, 2008-2010
- Mini Pascal Compiler: Designed a compiler including lexical analyzer, parser, and semantic analyzer (Java programming), 2010.
- Fingerprint Checker: Designed a fingerprint-based security system on AVR microprocessor (Embedded C programming using CodeVision AVR and simulation using Proteus), 2009
- PintOS: Implemented a thread scheduler and the capability to execute system functions and user programs (System-level C programming), 2008
- Single-Instruction CPU: Designed a one-instruction CPU in Verilog HDL with its own assembly syntax. All the regular RISC instruction set can be implemented using this single instruction, 2008